Avoiding or suppressing stray properties is often the goal of development work for semiconductor components. Particularly in the case of power semiconductor components, stray capacitances are often undesired.
In order to avoid for example undesired gate-drain capacitances, a lateral DMOS may be produced which achieves very good control of the gate-drain overlap region, and therefore the gate-drain capacitance, by way of self-aligned implantation of the LDD region at the gate electrode. The drain or the source is connected to the back side by way of a sinker. This leads to an increased output capacitance which results from the body region at source potential forming a pn junction both vertically with the drain sinker and laterally with the substrate at drain potential.